In synchronous digital communications systems, such as the SONET system or its European counterpart, SDH, asynchronous rate payload signals can be mapped into the synchronous SONET or SDH payload envelope. For example, asynchronous rate DS.sub.x (DS1, DS3, etc.) type signals can be mapped onto a SONET STS-1 payload envelope. In order to synchronize the SONET signals at an asynchronous node and still generate a smooth clock signal, pointers containing a byte or word of information (typically eight bits) are used to adjust the starting point of the next SONET payload envelope so that it can move relative to the SONET frame. For a DS3 data signal, for example, the pointer will advance the address in a write counter only when DS3 data signals are input. However, these pointer adjustments that stop and start the write address counter create phase "jumps" or "hits" that occur a periodically as "jitter" in a mapped output clock signal. Furthermore, if the DS3 signal is being mapped onto a SONET STS-1 payload, the jitter problem is worsened because the starting and stopping of the write counter occurs for STS-1 signals at eight unit intervals (i.e., produces 8 UI phase jumps). Consequently, jitter approaching 7 UI (peak to peak) can occur as a result of a single STS-1 pointer adjustment (an 8 UI step at the STS-1 rate produces a time gap of 8.times.19.3 ns=154 ns, or approximately 7 UI at the DS3 rate). This excessive jitter in the smoothed clock output signal retards the synchronization of downstream phase-locked loops and, therefore, produces significant time delays before the DS3 channel can again deliver reliable data. This synchronization problem severely degrades the overall reliability of the communications network.
A previously developed technique uses high-pass and low-pass filters to reduce a periodic jitter components in a clock signal being resynchronized. Specifically, U.S. Pat. No. 4,996,698, which is incorporated completely herein for all purposes, discloses a clock signal resynchronizing circuit for a SONET system. The clock signal is smoothed in a gradual manner by routing the portion of the signal containing the phase hit information through a high-pass filter, and summing the output of the high-pass filter with the stream of clock pulses to be smoothed. The combined signals are then processed through a phase-locked loop circuit, which functions as a low-pass filter to produce and maintain the smoothed clock output. Consequently, the phase hit clock signal information is removed from the clock signal stream being smoothed over a relatively long period of time, which reduces jitter to some extent in the smoothed clock output signal.
FIG. 1 depicts an existing clock signal resynchronizing circuit. The resynchronizer circuit illustrated in FIG. 1 is similar to that disclosed in U.S. Pat. No. 4,996,698. However, the specific details of a filter (identified herein as item 30) having performance characteristics similar to those of integrating filter 30 disclosed in U.S. Pat. No. 4,996,698, are shown herein to help facilitate understanding the present invention described below. Referring to FIG. 1, a portion of the incoming clock signal (PP or NP) representing phase hit information is routed through a high pass filter 12 and summed with the stream of clock pulses (CLK) to be smoothed. These combined (summed) signals are supplied to a phase-locked loop, which functions as a type two, second order low-pass filter. The phase-locked loop, which has a relatively high bandwidth, produces and maintains a smoothed clock output signal. Essentially, the phase hits are low pass-filtered by the phase-locked loop, and their effects on the smoothed clock output signal are introduced slowly over a relatively long period of time. An elastic buffer 18 is used to time-coordinate incoming data signals and the smoothed clock signals output from the resynchronizer circuit depicted generally as item 10.
Using the filter circuit depicted generally as item 30 in FIG. 1, the phase hit adjustments are made in one UI steps. In other words, the phase hits are "leaked out" from summer 16 to filter 30 at the rate of one bit at a time. Therefore, the bulk of the pointer adjustments (the remaining bits comprising the pointers) are not processed all at once through the phase-locked loop, which effectively reduces jitter. Nevertheless, the bit-leaking technique disclosed in FIG. 1 still produces unacceptable levels of jitter in the smoothed output clock signal, based on the stringent output payload jitter specifications required by users of today's high-speed digital communications systems. Furthermore, these relatively high levels of jitter compound resynchronization delays that occur in cascaded SONET channels.
A second existing technique for resynchronizing clock signals uses a complicated digital filter arrangement to leak out pointer adjustment data, one bit at a time, into a phase-locked loop. The magnitude of the resulting jitter can be reduced significantly by adjusting this digital filter's bandwidth and increasing its numerical resolution. Nevertheless, although the amount of jitter experienced using this technique may be reduced to a relatively low level, the digital circuitry that is employed is very complex and expensive to implement as an integrated circuit.